现代VLSI设计

出版时间：2006-2  出版社：高等教育  作者：沃尔夫  页数：604  

前言

　　This book was written in the belief that VLSI design is system design. Designing fastinverters is fun， but designing a highperformance， costeffective integrated circuitdemands knowledge of all aspects of digital design， from application algorithms tofabrication and packaging. Carver Mead and Lynn Conway dubbed this approach thetallthin designer approach. Todays hot designer is a little fatter than his or her 1979ancestor， since we now know a lot more about VLSI design than we did when Meadand Conway first spoke. But the same principle applies： you must be wellversed inboth highlevel and lowlevel design skills to make the most of your designopportunities.　　Since VLSI has moved from an exotic， expensive curiosity to an everyday necessity，universities have refocused their VLSI design classes away from circuit design andtoward advanced logic and system design. Studying VLSI design as a system designdiscipline requires such a class to consider a somewhat different set of areas than doesthe study of circuit design. Topics such as ALU and multiplexer design or advancedclocking strategies used to be discussed using TFL and boardlevel components， withonly occasional nods toward VLSI implementations of very large components.　　However， the push toward higher levels of integration means that most advanced logicdesign projects will be designed for integrated circuit implementation.　　I have tried to include in this book the range of topics required to grow and traintodays tall， moderatelychubby IC designer. Traditional logic design topics， such asadders and state machines， are balanced on the one hand by discussions of circuitsand layout techniques and on the other hand by the architectural choices implied byscheduling and allocation. Very large ICs are sufficiently complex that we canttackle them using circuit design techniques alone； the topnotch designer mustunderstand enough about architecture and logic design to know which parts of thecircuit and layout require close attention. The integration of systemlevel designtechniques， such as scheduling， with the more traditional logic design topics isessential for a full understanding of VLSIsize systems.

内容概要

　　《现代VLSI设计：片上系统设计（第3版改编版）》是一本介绍现代VLSI芯片设计过程的书籍，改编自PEARSONEDUCATION出版的Modern VLSI Design：System-on-Chip Design（3／e）一书。书中全面地论述了VLSI芯片设计的有关问题，反映了目前SoC的最新进展，并介绍了SoC的设计方法。全书共分10章。内容包括：数字系统与VLSl，晶体管的版图设计，逻辑门，组合逻辑网络，时序电路，子系统设计，自顶向下设计，系统设计，芯片设计，CAD系统及算法，另有3个附录。每章末尾均附有难度不同的习题。附录中还提供了丰富而实用的词汇表。改编者保持原书的风格和原有体系结构，根据国内的教学要求和课程设置，调整了原书的一些内容，使之更适合我国高等学校作为教材使用。　　《现代VLSI设计：片上系统设计（第3版改编版）》可作为高校电子工程、计算机科学与工程、微电子半导体等专业的高年级本科生和研究生的教材或教学参考书，也可供从事芯片设计的工程技术人员作为参考书使用。

书籍目录

Preface to the Third Edition ixPreface to the Second Edition xiPreface xiii1 Digital Systems and VLSI 11.1 Why Design Integrated Circuits? 11.2 Integrated Circuit Manufacturing 41.2.1 Technology 41.2.2 Economics 61.3 CMOS Technology 151.3.1 CMOS Circuit Techniques 151.3.2 Power Consumption 161.3.3 Design and Testability 171.4 Integrated Circuit Design Techniques 181.4.1 Hierarchical Design 191.4.2 Design Abstraction 221.4.3 Computer-Aided Design 281.5 A Look into the Future 301.6 Summary 311.7 References 311.8 Problems 322 Transistors and Layout 332.1 Introduction 332.2 Fabrication Processes 342.2.1 Overview 342.2.2 Fabrication Steps 372.3 Transistors 402.3.1 Structure of the Transistor 402.3.2 A Simple Transistor Model 452.3.3 Transistor Parasitics 482.3.4 Tub Ties and Latchup 502.3.5 Advanced Transistor Characteristics 532.3.6 Leakage and Subthreshold Currents 602.3.7 Advanced Transistor Structures 612.3.8 Spice Models 612.4 Wires and Vias 622.4.1 Wire Parasitics 652.4.2 Skin Effect in Copper Interconnect 722.5 Design Rules 742.5.1 Fabrication Errors 752.5.2 Scalable Design Rules 772.5.3 SCMOS Design Rules 792.5.4 Typical Process Parameters 832.6 Layout Design and Tools 832.6.1 Layouts for Circuits 832.6.2 Stick Diagrams 882.6.3 Layout Design and Analysis Tools 902.6.4 Automatic Layout 942.7 References 972.8 Problems 973 Logic Gates 1053.1 Introduction 1053.2 Static Complementary Gates 1063.2.1 Gate Structures 1063.2.2 Basic Gate Layouts 1103.2.3 Logic Levels 1133.2.4 Delay and Transition Time 1183.2.5 Power Consumption 1273.2.6 The Speed-Power Product 1303.2.7 Layout and Parasitics 1313.2.8 Driving Large Loads 1343.3 Switch Logic 1353.4 Alternative Gate Circuits 1363.4.1 Pseudo-nMOS Logic 1373.4.2 DCVS Logic 1393.4.3 Domino Logic 1413.5 Low-Power Gates 1463.6 Delay Through Resistive Interconnect 1523.6.1 Delay Through an RC Transmission Line 1523.6.2 Delay Through RC Trees 1553.6.3 Buffer Insertion in RC Transmission Lines 1593.6.4 Crosstalk Between RC Wires 1613.7 Delay Through Inductive Interconnect 1643.7.1 RLC Basics 1653.7.2 RLC Transmission Line Delay 1663.7.3 Buffer Insertion in RLC Transmission Lines 1673.8 References 1693.9 Problems 1714 Combinational Logic Networks 1774.1 Introduction 1774.2 Standard Cell-Based Layout 1784.2.1 Single-Row Layout Design 1794.2.2 Standard Cell Layout Design 1884.3 Simulation 1904.4 Combinational Network Delay 1944.4.1 Fanout 1954.4.2 Path Delay 1964.4.3 Transistor Sizing 2014.4.4 Automated Logic Optimization 2104.5 Logic and Interconnect Design 2114.5.1 Delay Modeling 2124.5.2Wire Sizing 2134.5.3 Buffer Insertion 2144.5.4 Crosstalk Minimization 2164.6 Power Optimization 2214.6.1 Power Analysis 2214.7 Switch Logic Networks 2254.8 Combinational Logic Testing 2294.8.1 Gate Testing 2314.8.2 Combinational Network Testing 2344.9 References 2364.10 Problems 2365 Sequential Machines 2415.1 Introduction 2415.2 Latches and Flip-Hops 2425.2.1 Categories of Memory Elements 2425.2.2 Latches 2445.2.3 Flip-Flops 2515.3 Sequential Systems and Clocking Disciplines 2525.3.1 One-Phase Systems for Flip-Flops 2555.3.2 Two-Phase Systems for Latches 2575.3.3 Advanced Clocking Analysis 2655.3.4 Clock Generation 2725.4 Sequential System Design 2735.4.1 Structural Specification of Sequential Machines 2735.4.2 State Transition Graphs and Tables 2755.4.3 State Assignment 2845.5 Power Optimization 2905.6 Design Validation 2915.7 Sequential Testing 2935.8 References 3005.9 Problems 3006 Subsystem Design 3036.1 Introduction 3036.2 Subsystem Design Principles 3066.2.1 Pipelining 3066.2.2 Data Paths 3086.3 Combinational Shifters 3116.4 Adders 3146.5 ALUs 3216.6 Multipliers 3226.7 High-Density Memory 3316.7.1 ROM 3336.7.2 Static RAM 3356.7.3 The Three-Transistor Dynamic RAM 3396.7.4 The One-Transistor Dynamic RAM 3406.8 References 3446.9 Problems 3447 Floorplanning 3477.1 Introduction 3477.2 Floorplanning Methods 3487.2.1 Block Placement and Channel Definition 3527.2.2 Global Routing 3587.2.3 Switchbox Routing 3607.2.4 Power Distribution 3617.2.5 Clock Distribution 3647.2.6 Floorplanning Tips 3697.2.7 Design Validation 3707.3 Off-Chip Connections 3717.3.1 Packages 3717.3.2 The I/O Architecture 3757.3.3 Pad Design 3767.4 References 3797.5 Problems 3818 Architecture Design 3878.1 Introduction 3878.2 Hardware Description Languages 3888.2.1 Modeling with Hardware Description Languages 3888.2.2 VHDL 3938.2.3 Verilog 4028.2.4 C as a Hardware Description Language 4098.3 Register-Transfer Design 4108.3.1 Data Path-Controller Architectures 4128.3.2ASM Chart Design 4138.4 High-Level Synthesis 4228.4.1 Functional Modeling Programs 4248.4.2 Data 4258.4.3 Control 4358.4.4 Data and Control 4418.4.5 Design Methodology 4438.5 Architectures for Low Power 4448.5.1 Architecture-Driven Voltage Scaling 4458.5.2 Power-Down Modes 4468.6 Systems-on-Chips and Embedded CPUs 4478.7 Architecture Testing 4538.8 References 4578.9 Problems 4579 Chip Design 4619.1 Introduction 4619.2 Design Methodologies 4619.3 Kitchen TimerChip 4709.3.1 Timer Specification and Architecture 4719.3.2 Architecture Design 4739.3.3 Logic and Layout Design 4789.3.4 Design Validation 4859.4 Microprocessor Data Path 4889.4.1 Data Path Organization 4899.4.2 Clocking and Bus Design 4909.4.3 Logic and Layout Design 4929.5 References 4949.6 Problems 49510 CAD Systems and Algorithms 49710.1 Introduction 49810.2 CAD Systems 49810.3 Switch-Level Simulation 49910.4 Layout Synthesis 50110，4，1 Placement 50310.4.2 Global Routing 50610.4.3 Detailed Routing 50810.5 Layout Analysis 51010.6 Timing AnalysisandOptimization 51210.7 Logic Synthesis 51710.7.1 Technology-Independent Logic Optimization 51810.7.2 Technology-Dependent Logic Optimizations 52510.8 Test Generation 52810.9 Sequential Machine Optimizations 53010.10 Scheduling and Binding 53210.11 Hardware/Software Co-Design 53410.12 References 53510.13 Problems 535A Chip Designers Lexicon 539B Chip Design Projects 557B.1 Class Project Ideas 557B.2 Project Proposal and Specification 558B.3 Design Plan 559B.4 Design Checkpoints and Documentation 562B.4.1 Subsystems Check 563B.4.2 First Layout Check 563B.4.3 Project Completion 563C Kitchen Timer Model 565C.1 Hardware Modeling in C 565C.I.1 Simulator 567C.1.2 Sample Execution 573References 577Index 593

章节摘录

　　A register-transfer simulator exhibits the correct cycle-by-cycle behavior atits inputs and outputs， but the internal implementation of the simulator mayhave nothing to do with the logic implementation. Several specialized languages for hardware description and simulation have been developed. Hardware simulation languages， such as VHDL and Vefilog， provide primitiveswhich model the parallelism of logic gate evaluation， delays， etc.， so that astructural description like a net list automatically provides accurate simulation. In a pinch， a C program makes a passable register-transfer simulator：the component is modeled as a procedure， which takes inputs for one cycleand generates the outputs for that cycle. However， hardware modeling in Cor other general-purpose programming languages requires more attention tothe mechanics of simulation.　　A logic simulator accepts a net list whose components are logic gates. Thesimulator evaluates the output of each logic gate based on the values pre-sented at the gates inputs. You can trace though the network to find logicbugs， comparing the actual value of a wire to what you think the valueshould be. Verilog and VHDL can be used for logic simulation： a libraryprovides simulation models for the logic gates； a net list tells the simulationsystem how the components are wired together.